1. Field of the Invention
The present invention relates to a reflective LCD (liquid crystal display), and particularly, to a reflective LCD having fine pixels formed on a semiconductor substrate with the pixels including first pixels (pixels A) arranged in first-pixel columns and second pixels (pixels B) arranged in second-pixel columns, the first- and second-pixel columns complementarily supplying a first fixed potential (well potential) and a second fixed potential (common potential) to each pixel in the first- and second-pixel columns.
2. Description of the Related Art
Projection-type large LCDs are widely used for outdoor public displays, control-board displays, high-vision-broadcast displays, SVGA computer displays, and the like.
The projection-type LCDs are largely classified into transmission LCDs and reflective LCDs. The transmission LCDs have a drawback. That is, a TFT (thin film transistor) provided for each pixel blocks light so that a transmission area transmitting light with respect to each pixel becomes smaller by area of the TFT. In other words, the numerical aperture of each pixel becomes smaller. For this reason, the reflective LCDs are attracting attention.
The reflective LCD mainly consists of a semiconductor substrate (Si substrate) on which MOSFETs (metal oxide semiconductor field effect transistors) serving as switching elements are connected to reflective pixel electrodes and hold capacitors, to form a matrix of pixels. Facing the reflective pixel electrodes, a transparent common electrode (counter electrode) serving for all pixels is formed on a transparent substrate (glass substrate). Between the semiconductor substrate and the transparent substrate, liquid crystals are sealed. Read light is made incident to the transparent substrate, and each potential difference between the common electrode and each reflective pixel electrodes is produced according to each video signal, to change alignments of the liquid crystals and thereby modulate the read light.
FIG. 1 is a sectional view showing a model of a pixel in a reflective LCD 10A according to a prior art, taken along orthogonal lines X and Y shown in FIG. 3.
FIG. 2A is a sectional view taken along a plane parallel to the surface of FIG. 1, showing a p− well region side, and FIG. 2B is a sectional view taken along a plane parallel to FIG. 1, showing a hold capacitor.
FIG. 3 is an enlarged plan view showing a model of a pixel in the reflective LCD 10A.
The reflective LCD 10A according to the prior art has many pixels to display images, and FIG. 1 shows one of the pixels. In FIG. 1, a semiconductor substrate 11 serves as a base and is a p-type (or n-type) substrate made of, for example, monocrystalline silicon (Si). The semiconductor substrate (hereinafter referred to as the p-type Si substrate) 11 has a p− well region 12, which is isolated in each pixel by left and right field oxide films 13A and 13B, as shown on the left side of the drawing. The p− well region 12 is provided with a switching element 14, which is a MOSFET.
The switching element (hereinafter referred to as the MOSFET) 14 has a gate oxide film 15 formed substantially at the center of the p− well region 12 and a polysilicon gate electrode formed on the gate oxide film 15, to provide a gate G.
On the left side of the gate G of the MOSFET 14, there is an LDD (lightly-doped drain) region 17A, which is a low-concentration n− impurity layer, and on the left side of the LDD region 17A, there is a source region 18, which is a high-concentration n+ impurity layer. On the source region 18, a source contact (source electrode) 19, which is aluminum wiring, is formed to provide a source S.
On the right side of the gate G of the MOSFET 14, there is an LDD region 17B, which is a low-concentration n− layer, and on the right side of the LDD region 17B, there is a drain region 20, which is a high-concentration n+ impurity layer. On the drain region 20, a drain contact (drain electrode) 21, which is aluminum wiring, is formed to provide a drain D.
The LDD regions 17A and 17B on both sides of the gate G of the MOSFET 14 function to relax voltage around the gate G.
On the right side of the p− well region 12 on the p-type Si substrate 11, a diffusion capacitor electrode 22 is formed by ion implantation. The electrode 22 is isolated in each pixel at the position shown in FIG. 1 by left and right field oxide films 13B and 13C. On the electrode 22, an insulating film 23 and a capacitor electrode 24 are formed in this order, to provide a hold capacitor C.
On the field oxide films 13A to 13C, gate electrode 16, and capacitor electrode 24, there are laminated a first interlayer insulating film 25, a first metal film 26, a second interlayer insulating film 27, a second metal film 28, a third interlayer insulating film 29, and a third metal film 30 in this order. The first, second, and third metal films 26, 28, and 30 are aluminum wiring formed in predetermined patterns.
The second metal film 28 blocks the read light L coming from a transparent substrate 33, to protect the p-type Si substrate 11 under the film 28. The film 28, therefore, will be referred to as the shading film 28.
The third metal film 30 is sectioned into a rectangle allocated for each pixel and functions as a reflective pixel electrode to reflect the read light L coming from the transparent substrate 33 and make the reflected light emanate from the transparent substrate 33. The film 30 will be referred to as the reflective pixel electrode 30.
On each reflective pixel electrode 30, a liquid crystal 31 is sealed. On the liquid crystals 31, a transparent common electrode (counter electrode) 32 is formed on the bottom surface of the transparent substrate (glass substrate) 33. Namely, the reflective pixel electrodes 30 and the transparent common electrode 32 face each other on opposite sides of the liquid crystals 31. The reflective pixel electrodes 30 are arranged in a matrix, and the transparent common electrode 32 serves for all reflective pixel electrodes 30. Namely, the common electrode 32 is not sectioned pixel by pixel.
The gate electrode 16 of the MOSFET 14 is connected to agate line 45 (FIGS. 3, 4A, and 4B), which is made of polysilicon and is integral with the gate electrode 16. The source contact (source electrode) 19 of the MOSFET 14 is connected to a signal line 41 (FIGS. 3, 4A, and 4B) arranged on the first metal film 26. The drain contact (drain electrode) 21 of the MOSFET 14 is connected to the reflective pixel electrode 30 through the first and second metal films 26 and 28. The capacitor electrode 24 of the hold capacitor C is connected to the reflective pixel electrode 30 through a capacitor electrode contact 34 made of aluminum wiring and the first and second metal films 26 and 28.
In FIG. 2A taken along a plane parallel to the surface of FIG. 1, a p+ electrode 35 is formed on the p− well region 12. On the p+ electrode 35, a well potential contact 36 is formed from aluminum wiring. The contact 36 is connected to a well line 42 (FIG. 3) on the first metal film 26.
In FIG. 2B taken along a plane parallel to the surface of FIG. 1, a common potential contact 37 is formed from aluminum wiring on the diffusion capacitor electrode 22 of the hold capacitor C. The contact 37 is connected to a common line 43 (FIG. 3) on the first metal film 26.
FIG. 3 is a plan view showing the pixel shown in FIG. 1.
In FIG. 3, the source contact (source electrode) 19, gate electrode 16, drain contact (drain electrode) 21 corresponding to the source S, gate G, and drain D of the MOSFET 14, respectively, are horizontally aligned at an upper left part of FIG. 3. Below the upper left part, the large rectangular diffusion capacitor electrode 22 of the hold capacitor C is arranged. Consequently, the rectangular reflective pixel electrode 30 occupies a large area.
The signal line 41 connected to the source contact (source electrode) 19, the well line 42 connected to the well potential contact 36, and the common line 43 connected to the common potential contact 37 are also connected to other pixels that are arranged in the same column where the pixel of FIG. 3 is arranged. Between the signal line 41 and the well line 42, a connection line 44 that is connected to the drain contact 21 located thereabove and the lower capacitor electrode contact 34 located therebelow runs substantially in parallel with the signal line 41, well line 42, and common line 43 within the area of the pixel in question. The gate line 45 connected to the gate electrode 16 is also connected to other pixels that are arranged in the same row where the pixel in question is present.
According to the reflective LCD 10A of the prior art, a plurality of pixels each having the structure of FIG. 1 are arranged in columns and rows to form a matrix on the p-type Si substrate 11. An active matrix drive circuit 50A is provided for driving such a matrix of pixels. The drive circuit 50A will be explained with reference to FIGS. 4A and 4B.
FIG. 4A is a block diagram explaining the active matrix drive circuit 50A for the reflective LCD 10A, and FIG. 4B shows a model of a transistor part of the drive circuit 50A.
According to the active matrix drive circuit 50A shown in FIGS. 4A and 4B for the reflective LCD 10A of the prior art, the MOSFET (switching element) 14, the reflective pixel electrode 30 connected to the MOSFET 14, and the hold capacitor C connected to the MOSFET 14 form a pixel. The pixels are arranged in columns and rows to form a matrix on the p-type Si substrate (semiconductor substrate) 11. As shown in FIG. 1, the common electrode 32 formed on the transparent substrate 33 faces the reflective pixel electrodes 30, and the liquid crystals 31 are sealed between the reflective pixel electrodes 30 and the common electrode 32.
To specify one of the pixels, a horizontal shift register circuit 51 is extended in a horizontal (left-to-right) direction and a vertical shift register circuit 54 is extended in a vertical (top-to-bottom) direction.
From the horizontal shift register circuit 51, the signal lines 41 are vertically extended for the pixel columns, respectively, through video switches 52. For the sake of simplicity, FIG. 4A shows only one signal line 41 extended from the circuit 51. Between the circuit 51 and the video switch 52, the signal line 41 is connected to a video line 53. Each signal line 41 is connected to the source electrodes 19 of the MOSFETs 14 arranged in the column to which the signal line 41 is assigned.
From the vertical shift register circuit 54, the gate lines 45 are horizontally extended for the pixel rows, respectively. For the sake of simplicity, FIG. 4A shows only one gate line 45 extended from the circuit 54. Each gate line 45 is connected to the gate electrodes 16 of the MOSFETs 14 arranged in the row to which the gate line 45 is assigned.
The drain electrode 21 of the MOSFET 14 is connected to the capacitor electrode 24 of the hold capacitor C and the reflective pixel electrode 30. The active matrix drive circuit 50A employs a known frame inversion drive technique that alternates video signals between positive and negative polarities frame by frame. For example, video signals in a frame period n are in a positive write period and those in a frame period n+1 are in a negative write period. To pass a video signal, the signal line 41 is connected to the source electrode 19 or drain electrode 21 of the MOSFET 14. In this example, the signal line 41 is connected to the source electrode 19 as mentioned above. If the signal line 41 is connected to the drain electrode 21, the source electrode 19 is connected to the capacitor electrode 24 of the hold capacitor C and the reflective pixel electrode 30.
The reflective LCD 10A of the prior art must supply a first fixed potential (hereinafter referred to as the well potential) to the MOSFET 14 and a second fixed potential (hereinafter referred to as the common potential) to the hold capacitor C.
The well potential (first fixed potential) to the MOSFET 14 is a fixed potential, for example, a voltage of 0 V and is supplied between the gate line 45 and the well line (first fixed potential line) 42. The well line 42 is connected to the well potential contact 36 (FIGS. 2A and 3) on the p+ electrode 35 (FIG. 2A) formed in the p− well region 12. When an n− well region is employed, a well potential of, for example, 15 V may be employed.
The common potential (second fixed potential) to the hold capacitor C is a fixed potential, for example, a voltage of 8.5 V and is applied between the capacitor electrode 24 of the hold capacitor C and the common line (second fixed potential line) 43. The common line 43 is connected to the common potential contact 37 (FIGS. 2B and 3) formed on the diffusion capacitor electrode 22. The common potential may have an optional voltage value to form the hold capacitor C. It may preferably be set to a center value (for example, 8.5 V) of a video signal, so that a voltage applied to the hold capacitor C may be half a source voltage. In this case, a hold capacitor withstand voltage can be half the source voltage, to make the insulating film 23 (FIG. 1) of the hold capacitor C thinner and increase capacitance. The larger the capacitance of the hold capacitor C, the more the potential on the reflective pixel electrode 30 is stabilized to prevent flickering and burning. The hold capacitor C accumulates charge according to a potential difference between the potential applied to the reflective pixel electrode 30 and the common potential, holds the accumulated voltage during an OFF state of the MOSFET 14 or an unselected period, and continuously applies the held voltage to the reflective pixel electrode 30.
To selectively drive one of the pixels by the active matrix drive circuit 50A of the reflective LCD 10A according to the prior art, video signals are sequentially supplied to the video line 53, and one of the video signals is supplied to one signal line 41 through the video switch 52. Then a MOSFET 14 positioned at an intersection of the signal line in question and a selected gate line 45 is turned on to drive the pixel.
The video signal is supplied through the signal line 41 to the selected reflective pixel electrode 30 and is written, as charge, into the hold capacitor C. At the same time, a potential difference is produced between the reflective pixel electrode 30 and common electrode 32 in response to the video signal, to modulate the optical characteristic of the liquid crystal 31. Consequently, the read light L (FIG. 1) coming from the transparent substrate 33 is modulated pixel by pixel in the liquid crystal 31, the modulated light is reflected by the reflective pixel electrode 30, and the reflected light is emitted outside from the transparent substrate 33. Therefore, unlike the transmission LCD, the reflective LCD can utilize nearly 100% of the read light L (FIG. 1), to provide finer and brighter images.
As explained with reference to FIG. 3, the reflective LCD 10A according to the prior art must arrange three lines, i.e., the signal line 41, well line 42, and common line 43 on the first metal film 26 (FIG. 1) for each pixel column to connect pixels therein. These lines or wires on the first metal film 26 (FIG. 1) make it difficult to reduce the size of each pixel. As a result, the reflective LCD 10A according to the prior art involves a matrix of large pixels on the p-type Si substrate 11.